The present invention relates to the manufacture of substrates. More particularly, the invention provides techniques including an apparatus and system software for processing substrates using a cluster tool apparatus with plasma immersion ion implantation ("PIII"). The present cluster tool apparatus with PIII can be used for the manufacture of a variety of substrates such as a silicon-on-insulator substrates for semiconductor integrated circuits, for example. Additionally, the present cluster tool apparatus can be generally used for the manufacture of integrated circuits. But it will be recognized that the invention has a wider range of applicability; it can also be applied to other substrates for multi-layered integrated circuit devices, three-dimensional packaging of semiconductor devices, photonic devices, piezoelectronic devices, microelectromechanical systems ("MEMS"), sensors, actuators, epitaxial-like substrates using similar or dis-similar materials, solar cells, flat panel displays (e.g., LCD, AMLCD), biological and biomedical devices, and the like.
As device size becomes smaller and wafer size becomes larger, it has been desirable to fabricate integrated circuits on multi-layered substrates such as a silicon-on-insulator ("SOI") substrate or wafer, rather than conventional "bulk" silicon wafers. A variety of techniques have been proposed or used for fabricating the SOI wafer. These techniques include, among others, bonding a thick film of silicon material onto an insulating layer formed overlying a bulk substrate. The thick film of silicon material is commonly "thinned" by way of grinding and polishing techniques such as chemical mechanical planarization. Although this technique is fairly easy to useful in making an SOI wafer, the technique is extremely time consuming. Additionally, the technique is extremely expensive due to the use of the grinding or polishing technique, which often takes a long time and uses expensive processing chemicals. Grinding has also been shown to degrade device performance. Accordingly, an SOI wafer made by way of conventional bonding and grinding techniques are extremely costly and have numerous limitations.
A technique called "separation by implantation of oxygen," commonly termed SIMOX also has been proposed. A detailed description of this process is described in Stanley Wolf Ph.D., SILICON PROCESSING FOR THE VLSI ERA (Volume 2), pages 66-79, which is hereby incorporated by reference. This technique generally uses conventional beam-line ion implanters for introducing the oxygen into the silicon wafer. Unfortunately, the conventional SIMOX process generally produces a costly resulting SOI wafer. This cost often stems from the long time needed to implant a sufficient dose of oxygen into the silicon wafer. Since ion implanters commonly represent one of the largest capital cost items in a fabrication facility, it is often difficult to allocate the implanter for use in the conventional SIMOX process, which is often used for a variety of other integrated circuit processing operations. Additionally, many fabrication facilities (e.g., integrated circuit and wafer) simply cannot afford purchasing additional ion implantation equipment due to its excessive cost. Accordingly, silicon-on-insulator wafers made using the conventional SIMOX process are often costly and generally take a long time to fabricate.
From the above, it is seen that techniques for the manufacture of substrates that are cost effective and efficient are often desirable.